Design of Low Power Half Adder using Static 125nm CMOS Technology
نویسندگان
چکیده
منابع مشابه
Low-Power Adder Design for Nano-Scale CMOS
A fast low-power 1-bit full adder circuit suitable for nano-scale CMOS implementation is presented. Out of the three modules in a common full-adder circuit, we have replaced one with a new design, and optimized another one, all with the goal to reduce the static power consumption. The design has been simulated and evaluated using the 65 nm PTM models.
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ژورنال
عنوان ژورنال: International Journal of Engineering and Technical Research (IJETR)
سال: 2018
ISSN: 2321-0869,2454-4698
DOI: 10.31873/ijetr.8.9.61